62 lines
1.5 KiB
C
62 lines
1.5 KiB
C
#include <apic.h>
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#include <int.h>
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#include <msr.h>
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#include <debug.h>
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#include <mem.h>
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#define APIC_MSR_ENABLE 0x800
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#define APIC_BASE 0xFEE00000
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#define R_ID 0x020
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#define R_VERSION 0x030
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#define R_EOI 0x0B0
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#define R_LDR 0x0D0
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#define R_SPURIOUS 0x0F0
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#define R_INT_CMD_LO 0x300
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#define R_INT_CMD_HI 0x310
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#define R_TIMER_LVT 0x320
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#define R_THERMAL_LVT 0x330
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#define R_PERF_LVT 0x340
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#define R_LINT0_LVT 0x350
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#define R_LINT1_LVT 0x360
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#define R_ERROR_LVT 0x370
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#define LVT_MASKED 0x10000
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#define SPURIOUS_LVT_ENABLED 0x100
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#define APIC(reg) apic[reg/4]
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uint32_t volatile *apic = P2V(APIC_BASE);
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void apic_interrupt(uint8_t destination, uint8_t level, uint8_t type, uint8_t vector)
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{
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uint64_t data = ((level & 0x1)<<14) | ((type & 0x7)<<8) | vector;
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APIC(R_INT_CMD_HI) = destination << 24;
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APIC(R_INT_CMD_LO) = data;
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}
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void apic_ack()
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{
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APIC(R_EOI) = 0;
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}
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void apic_init()
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{
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debug_info("APIC - APIC_BASE MSR: %x\n", msr_read(MSR_APIC_BASE));
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// Enable APIC by setting the enable bit in the APIC MSR
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msr_write(MSR_APIC_BASE, msr_read(MSR_APIC_BASE) | APIC_MSR_ENABLE);
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// Make sure the APIC base addres is mapped in kernel memory
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vmm_set_page(0, (uintptr_t)P2V(APIC_BASE), APIC_BASE, PAGE_PRESENT | PAGE_WRITE);
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debug_info("APIC - ID: %x\n", APIC(R_ID));
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debug_info("APIC - Version: %x\n", APIC(R_VERSION));
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uint8_t id = APIC(R_ID) >> 24;
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if(id <= 0)
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APIC(R_LDR) = 1 << (24 + id);
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APIC(R_SPURIOUS) = SPURIOUS_LVT_ENABLED | INT_APIC_SPUR;
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APIC(R_EOI) = 0;
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}
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