Enable SSE

src/kernel/cpu/cpu.c

@@ -27,4 +27,5 @@ void cpu_init() {
   apic_init();
   ioapic_init();
   timer_init();
+  sse_init();
 }

src/kernel/cpu/sse.S

@@ -0,0 +1,30 @@
+.intel_syntax noprefix
+
+.global sse_init
+sse_init:
+  //; Enable bits 9 and 10 in cr4
+  //; 9: Enable SSE instructions
+  //; 10: Enable SSE exceptions
+  mov rax, cr4
+  or rax, 1<<9 | 1<<10
+  mov cr4, rax
+
+  //; Set bit 1 and unset bit 2 in cr0
+  //; 1: Coprocessor monitoring
+  //; 2: Coprocessor emulation
+  mov rax, cr0
+  or rax, 1<<1
+  and rax, ~(1<<2)
+  mov cr0, rax
+
+  ret
+
+.global sse_save
+sse_save:
+  fxsave [rdi]
+  ret
+
+.global sse_restore
+sse_restore:
+  fxrstor [rdi]
+  ret

src/kernel/include/cpu.h

@@ -99,3 +99,8 @@ void ioapic_init();
 
 // cpu/timer.c
 void timer_init();
+
+// cpu/sse.S
+void sse_init();
+void sse_save(void *addr);
+void sse_restore(void *addr);

src/kernel/include/proc.h

@@ -7,6 +7,7 @@ struct process {
   uint64_t state;
   uint64_t P4;
   struct process *q_next;
+  void *sse;
   uint8_t stack[];
 };
 

src/kernel/proc/process.c

@@ -1,6 +1,7 @@
 #include <stdint.h>
 #include <proc.h>
 #include <memory.h>
+#include <stdlib.h>
 
 struct swtch_stack {
   uint64_t RBP;
@@ -24,6 +25,10 @@ struct process *new_process(void (*function)(void)) {
   p->q_next = 0;
   p->P4 = new_P4();
 
+  // Storage for SSE registers must be 16 byte aligned
+  void *sse = malloc(512+15);
+  p->sse = (void *) (((uintptr_t)sse + 15) & ~0xF);
+
   struct swtch_stack *stck = p->stack_ptr;
   stck->RBP = (uint64_t)&stck->RBP2;
   stck->ret = (uint64_t)function;

src/kernel/proc/scheduler.c

@@ -32,8 +32,11 @@ void scheduler() {
 
     current_proc = new;
     write_cr3(new->P4);
+    sse_restore(current_proc->sse);
+
     switch_stack(&scheduler_proc->stack_ptr, &new->stack_ptr);
 
+    sse_save(current_proc->sse);
     scheduler_insert(current_proc);
     current_proc = 0;
   }