174 lines
6.2 KiB
Markdown
174 lines
6.2 KiB
Markdown
layout: post
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title: "Z80 Tester"
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subtitle: "Bouncing buttons"
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tags: [electronics]
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In the [last post](/blog/2013/01/Z80-Information/) I said we only needed two
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pieces of support circuits to get a Z80 running, namely a clock and a
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reset circuit.
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Let's take a look at the most advanced one first; the clock signal
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generator.
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{: .right}
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Clock signal
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------------
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The Z80 needs a 5V square clock signal.
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For testing purposes it's ok to generate the clock signal by hand. The
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easiest way to do this requires only a switch and a resistor configured
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like the figure on the right.
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Let me just stop you right now and tell you that this won't work.
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Why? Well, take a look at the output in an oscilloscope:
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Doesn't look so bad, does it? Well, let's take a closer look at that
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falling edge to the left. Here it is, zoomed in about 250 times:
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Now that's not pretty. If you used this clock circuit, for every time
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you press the button, the Z80 will receive a dozen pulses or two. That
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makes for some very unrepeatable behavior, and repeatability is what
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computers are all about.
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{: .right}
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A better clock signal
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---------------------
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Here's a good clock generator. It requires two switches which are pushed
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alternately, two pull-up resistors and two NAND gates (e.g. 74HC00).
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This is what's called an S-R-latch (S-R is short for Set-Reset).
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Let's say the clock output is currently HIGH (+5V) and that no switches
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are pressed. The upper NAND gate then has two HIGH inputs, which means
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its output is LOW (0V). The lower NAND has one LOW input and one HIGH,
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which means its output is HIGH. By pushing the top button, one of the
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inputs to the top NAND is grounded so that its input is (LOW, HIGH)
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which means it outputs HIGH. This means the lower NAND gets the input
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(HIGH, HIGH) which makes its output LOW and when the button is released,
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the top NAND will have the input (HIGH, LOW) and thus still output HIGH.
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It's a bit simpler to understand if you just think about it than if you
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try to read my messy explanation, but you must assume that the clock
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signal is either HIGH or LOW before you start thinking.
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{: .left}
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Anyway, I built this circuit on a bread board and measured it the same
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way as the last one.
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Nice and clean. We've got our clock source.
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Reset switch
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------------
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When it comes to reset the Z80 is not as picky as with the clock signal.
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In fact, we can use the first attempt at a clock signal for reset.
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The internal reset circuitry of the Z80 depends on the clock signal,
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so as long as the clock doesn't move, whatever happens with the reset
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signal doesn't matter.
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This fact is important to rember for other reasons too; to perform a
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reset, the reset pin must be pulled low for a few clock cycles.
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In other words: To perform a reset, push the reset button, toggle the
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clock a handful of times (minimum three), release the reset button.
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That took me a while to figure out and is why you should always read
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your datasheets carefully, kids.
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A similar note of caution: Don't leave the clock signal in its LOW state
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for any extended periods of time or the Z80 will forget its state. To be
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sure, always make the clock HIGH right after making it LOW. You could
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add an LED to show its current state.
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Let's wire it up
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Z80 tester
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----------
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Here's a Z80 tester circuit wired up on my breadboard.
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The connections are as follows:
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- `D0`-`D7` are pulled low through resistors of ~1kΩ.
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- `/INT`, `/NMI`, `/WAIT` and `/BUSRQ` are connected to +5V.
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- `+5V` and `GND` are connected as labeled.
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- `/RESET` is connected to a pull up resistor and a button as described
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above.
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- `CLK` is connected to an Arduino nano which generates a 500 Hz square
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signal (I felt a bit lazy).
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- `A0`-`A7` are connected to the logic probes of my oscilloscope.
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But before I power this up, let's think about what we're expecting to see.
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As we release the reset button (after keeping it down for three clock
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cycles or more) the Z80 starts to read instructions at address `0x0000`.
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Since all data pins are permanently tied low it will read the value
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`0x00` which corresponds to a `NOP` instruction. This means it skips
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ahead to address `0x0001` to read its next instruction and so on.
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In other words, we expect the 8 lowest address lines to count upwards
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binarily from 0 to 255. Since there are 8 address lines we're not
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monitoring, it should make this count 255 times before getting back to
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address `0x0000` again. But we won't be able to see the difference
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between the counts.
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Ok, let's take a look.
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Just like that. This Z80 seems to be working fine.
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All 255 addresses didn't quite fit in this picture, but you can see
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address `0xXX00` to the left and `0xXX7B` to the right.
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Scrolling forwards a bit in time we find something interesting.
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See that thing on `A7`? It's not stable, but is pulsing. The same
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behavior can be seen on `A8`-`A15`. But why?
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Dynamic memory refresh, that's why.
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As I described in the last post; right after fetching an instruction,
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the Z80 sends a refresh pulse to the memory chips. During this pulse, it
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also sends an address on the 7 lowest address lines, i.e. `A0`-`A6`. The
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other address lines are pulled low.
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Let's take a closer look at the signals used.
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Here I also connected to the oscilloscope
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- `/M1`
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- `/MREQ`
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- `/RD`
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- `CLK`
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We can clearly see the instruction fetch cycle. `/M1` goes low, followed
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by `/MREQ` and then `/RD`. Then all three goes high while the processor
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is decoding the instruction.
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During the decode cycle, we see `/MREQ` go low again. This is the memory
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refreshing. I didn't connect the `/RFSH` line to the oscilloscope but,
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trust me, it goes low at about the same time.
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Next is the execute cycle, which for the `NOP` instruction is nothing at
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all, so the processor jumps right to the next instruction fetch cycle.
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Ok... so the Z80 is indeed working as expected.
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Next time we'll look at a control panel.
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